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Webinar by 松澤先生

Title: Webinars for Young Excellence: Interpolation: Creating a reference free smooth A/D conversion Presenter: Prof. Akira Matsuzawa Abstract: Conventional A/D conversion is performed by comparing the input signal voltage with the reference voltage. On the other hand, by dividing and comparing the output voltages of two amplifiers with different reference voltages with the same input signal voltage, it was found that A/D conversion can be performed. This A/D conversion method is called interpolated A/D conversion. This conversion method enables smooth A/D conversion with a small DNL without adjusting the gain of the amplifier or the reference voltage, and also enables low power consumption by reducing the number of amplifiers. In this talk, we will introduce not only the principles and effects of interpolated A/D conversion, but also conceptual methods in circuit development, such as generalization by intuition and formulation that gave rise to unique A/D conversion methods. A resistive-interpolated Bi-CMOS ADC was developed for home HDTV receivers. A capacitive-interpolated CMOS ADC reduced the power consumption to 1/8 of other ADCs was developed for the portable digital video equipment such as a handy camcorder. A gate-width interpolation CMOS ADC achieved ultra-high-speed operation of 400 MS/s and 1/10 the power consumption of the other ADCs. It is embedded on the world’s first one-chip Mixed Signal SoC for DVD and contributed higher performance and lower cost of DVD recorders. In this talk, we would like you to understand that the interpolated A/D conversion method is not just an idea but was created for the development of A/D converters with high performance and low power in order to realize the new electronic devices. Akira Matsuzawa received B.S., M.S., and Ph.D. degrees in EE from Tohoku University, Sendai, Japan, in 1976, 1978, and 1997. In 1978, he joined Panasonic, and in 2003, joined Tokyo Institute of Technology as a full professor, and in 2018, became professor emeritus and CEO of Tech Idea. He has been developing video-rate ADCs, mixed-signal SoCs and millimeter-wave CMOS transceivers. In 2022, he received IEEE Donald. O. Pederson award in Solid-State Circuits. He is an IEEE Fellow since 2002 and Life-Fellow since 2023.
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ホームページリニューアル

ホームページをリニューアルしました。 Hugo+Static CMS+Github+Github Actionsで動いています。流行り?のSSG(Static Site Generation)にしてみました。 Decap CMS (旧Netlify CMS)は、最近v3になって日本語編集がまともになりましたが、結局、Static CMSにしてみました。
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卒業式

修士修了おめでとうございます!引き続き博士課程でも頑張ってください!
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Prof. Bogdan Staszewski

6/9、University College DublinのBogdan Staszewski先生が東工大に訪問され、最新の研究内容についてご講演頂きました.
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Prof. Kenneth O

6/7、テキサス大学ダラス校のKenneth O先生が東工大に訪問され、最新の研究内容についてご講演頂きました
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Prof. Donald Lie

3/29、テキサス工科大学のDonald Lie先生が東工大に訪問され、最新の研究内容についてご講演頂きました。
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新アーキテクチャのデジタル位相同期回路を開発

要点 新しい非均一オーバーサンプリング手法を用いたデジタル位相同期回路を開発。 雑音の大きいサンプリング領域を排除し、位相同期回路のジッタを大幅に低減。 デジタル機器の小型化・低消費電力化を実現し、IoT向けLow-Power Beyond 5Gデバイスの普及を加速。
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ISSCCでOB会

松澤先生のISSCCのPlenary講演のあと、研究室の現役+OBで40名ぐらい集まりました!
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ISSCC 2023で6件発表

ISSCC 2023で発表します! Regular Session Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration” Dongwon You, et al., “A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler” Xi Fu, et al., “A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low Earth Orbit Small Satellite Constellation” Plenary Talk Prof. Matsuzawa, “Shape the World With Mixed-Signal Integrated Circuits – Past, Present, and Future” Chun WangさんとDingxin Xuさんが、Student Research Previewで発表します。
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