Latest News

Prof. Dr. Vadim Issakov (Technische Universität Braunschweig) came to our lab at Nov. 21st, 2023!

We had a celebration party for Prof. Matsuzawa and Prof. Okada, and more than 90 alumni and guests attended the party. Prof. Masu (Tokyo Tech President) Prof. Dosho (First-graduated doctor) Prof. Miyahara (past Assistant Professor) Prof. Motomura Prof. Ikeda (guest from University of Tokyo) Mr. Yamazaki (doctoral student)

Congratulations!! Chun Wang-san and Dinxin Xu-san!!

Title: Webinars for Young Excellence: Interpolation: Creating a reference free smooth A/D conversion Presenter: Prof. Akira Matsuzawa Abstract: Conventional A/D conversion is performed by comparing the input signal voltage with the reference voltage. On the other hand, by dividing and comparing the output voltages of two amplifiers with different reference voltages with the same input signal voltage, it was found that A/D conversion can be performed. This A/D conversion method is called interpolated A/D conversion. This conversion method enables smooth A/D conversion with a small DNL without adjusting the gain of the amplifier or the reference voltage, and also enables low power consumption by reducing the number of amplifiers. In this talk, we will introduce not only the principles and effects of interpolated A/D conversion, but also conceptual methods in circuit development, such as generalization by intuition and formulation that gave rise to unique A/D conversion methods. A resistive-interpolated Bi-CMOS ADC was developed for home HDTV receivers. A capacitive-interpolated CMOS ADC reduced the power consumption to 1/8 of other ADCs was developed for the portable digital video equipment such as a handy camcorder. A gate-width interpolation CMOS ADC achieved ultra-high-speed operation of 400 MS/s and 1/10 the power consumption of the other ADCs. It is embedded on the world’s first one-chip Mixed Signal SoC for DVD and contributed higher performance and lower cost of DVD recorders. In this talk, we would like you to understand that the interpolated A/D conversion method is not just an idea but was created for the development of A/D converters with high performance and low power in order to realize the new electronic devices. Akira Matsuzawa received B.S., M.S., and Ph.D. degrees in EE from Tohoku University, Sendai, Japan, in 1976, 1978, and 1997. In 1978, he joined Panasonic, and in 2003, joined Tokyo Institute of Technology as a full professor, and in 2018, became professor emeritus and CEO of Tech Idea. He has been developing video-rate ADCs, mixed-signal SoCs and millimeter-wave CMOS transceivers. In 2022, he received IEEE Donald. O. Pederson award in Solid-State Circuits. He is an IEEE Fellow since 2002 and Life-Fellow since 2023.

Okada Laboratory’s website has been renewed!

Yamazaki-san won IEEE SSCS Japan Chapter VDEC Design Award!!

Prof. Inchan Ju visited our lab!

Congratulations on completing your Master’s degree! Keep up the good work in your PhD study!

Xi FU, a doctoral course student, won this-year’s IEEE SSCS Predoctoral Achievement Award. This award is for recognizing his outstanding achievement based on the aveacademic record and promise, quality of publications.

New transceiver design capable of both transmission and reception at frequencies over 100 GHz and at 112 Gb/s data rate could pave the way to 6G technologies, as reported by scientists at Tokyo Tech. By effectively suppressing the self-interference caused by the transmission signal leaking into the receiver, the proposed architecture reaches unprecedented data rates while maintaining a surprisingly compact size.

Prof. Bogdan Staszewski came to our lab at June 9th, 2023! Welcome!!!

Prof. Kenneth O came to our lab at June 7th, 2023! Welcome!!!

Dr. Bodhisatwa Sadhu, from IBM, visited our laboratory! Thank you! image

Prof. Donald Lie came to our lab at March 29th, 2023! Welcome!!!

Cherry-blossom viewing!

Jitters are a common shortcoming of modern electronic devices using a high-frequency digital signal. While oversampling phase-locked loops (OSPLLs) can expand the loop bandwidth, effectively reducing jitter, conventional OSPLLs suffer from high jitter in noisy signal peak areas. Tokyo Tech researchers have instead suggested and demonstrated a non-uniform OSPLL that can efficiently suppress jitter through adaptive loop gain calibration. This novel architecture leads to more economical and power-efficient devices than conventional OSPLLs.

More than 40 lab members and alumni gathered after ISSCC plenary talk by Prof. Matsuzawa!

Publication in ISSCC 2023. Regular Session Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration” Dongwon You, et al., “A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler” Xi Fu, et al., “A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low Earth Orbit Small Satellite Constellation” Plenary Talk Prof. Matsuzawa, “Shape the World With Mixed-Signal Integrated Circuits – Past, Present, and Future” Chun Wang and Dingxin Xu will present their work in Student Research Preview.

Prof. Emanuel Cohen came to our lab at November 29th, 2022! Welcome!!!

Publication in ISSCC 2022. Regular Session Jian Pang, et al., “A Power-Efficient 24-71GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36-dB Inter-Band Blocker Rejection for 5G NR” Xi Fu, et al., “A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation” Michihiro Ide and Dongwon You will present their work in Student Research Preview.