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3 presentations in VLSI Symposium

Chenxin Liu, Sena Kato, Yi Zhang presented their work. IEEE Symposium on VLSI Technology & Circuits Chenxin Liu “A 640-Gb/s 4x4-MIMO D-Band CMOS Transceiver Chipset” Sena Kato “A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer” Yi Zhang “A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond”
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A Novel 640 Gbps Chipset Paves the Way for Next Generation Wireless Systems

A new D-band CMOS transceiver chipset with 56 GHz signal-chain bandwidth achieves the highest transmission speed of 640 Gbps for a wireless device realized with integrated circuits, as reported by researchers from Tokyo Tech and National Institute of Information and Communications Technology. The proposed chipset is highly promising for the next generation of wireless systems.
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MCRG Technical Meeting

MCRG Technical Meeting was held. Due to the Corona disaster, it had been 4 years and 3 months since the last face-to-face meeting was held on 2020/1/16. 5/24(Fri) 17:30-18:30 Invited talk @ S4-202 (S422) 環境社会理工学院 笠井 康子先生 「月に行ってテラヘルツ波で観測しよう! TSUKIMI: Lunar Terahertz SUrveyor for KIlometer-scale MappIng」 18:30- ポスターセッション @ S4-203 (S423) Zijie LIANG (Prof. Fukawa lab) Slotted Unsourced Random Access Using Massive MIMO over Frequency Selective Channels Kui WANG (Prof. Sakaguchi lab) Smart Mobility Digital Twin for Automated Driving Futo NODA (Prof. Tran lab) Proposal of LEO based Population Estimation System using Smartphone Emitted WLAN Signals Zhou DERUN (Prof. Takada lab) Prediction of Shadowing Loss of 2D Object by Mirror Kirchhoff Approximation with Unequal Interval Yaxiang WU (Prof. Hirokawa lab) Millimeter-Wave Slot Array Antennas using Gap Waveguides and Perpendicular Corporate-Feed Parallel Plates for Simplified Fabrication Chun WANG (Prof. Okada lab) 300GHz-band 4-Element Amplifier-Last Phased-Array Transmitter
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Prof. Wei Deng and Prof. Xiang Gao

Prof. Wei Deng (SSCS DL, Tsinghua University) and Prof. Xiang Gao (Zhejiang University) visited Tokyo Tech! 5/2(Thu) 15:30-16:30 Prof. Wei Deng (SSCS DL) “Joint Radar-communication CMOS Transceiver” 16:30-17:30 Prof. Xiang Gao “Frac-N Sampling PLL with Phase Detection and Quantization Noise Cancellation in a Single Ramp Generation” ★Details of each talk (Talk 1) Speaker: Prof. Wei Deng (Tsinghua University) Title: Joint Radar-communication CMOS Transceiver: From System Architecture to Circuit Design Abstract: Recent years, millimeter-wave and Terahertz radar systems for sensing and radio systems for communication have attracted substantial attention both from the academia and industry. In addition, there is an increasing demanding for fusing both the hardware platform and frequency band of the radar and radio system, which has advantages of energy efficiency, performance optimization, spectrum sharing/efficiency, compact size, interference management, and the overall cost, as compared to assembling of two distinct systems. This lecture will introduce the current and future trends in the emerging joint radar-communication CMOS transceiver from system architecture to circuit design. Bio: Wei Deng received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China (UESTC), China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. He was with Apple Inc., Cupertino, CA, USA, working on RF, mm-wave, and mixed-signal IC design for wireless transceivers and Apple A-series processors. Currently he is with Tsinghua University, Beijing, China, as an Associate Professor. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and systems for wireless communications, sensing, and imaging systems. He has authored or co-authored more than 160 IEEE journal and conference articles. Dr. Deng is a TPC Member of ISSCC, VLSI, A-SSCC, CICC and ESSCIRC. He has been an Associate Editor and a Guest Editor of the IEEE Solid-State Circuits Letters (SSC-L), a Guest Editor of the IEEE Journal of Solid-state Circuits (JSSC), and a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS). (Talk 2) Speaker: Prof. Xiang Gao (Zhejiang University) Title: Frac-N Sampling PLL with Phase Detection and Quantization Noise Cancellation in a Single Ramp Generation Abstract: Conventional PLLs detecting phase error in the time domain using a phase frequency detector often suffer from poor in-band phase noise due to the limited phase detector (PD) gain. The (Sub-)Sampling PLL is becoming a popular low jitter PLL architecture due to high gain of the SSPD. However, the high gain SSPD has a limited linear detection range, which is a challenge in fractional-N operation with the quantization noise. This talk presents a SPLL design with a merged constant-slope digital-to-time converter(DTC) and sampling phase detector (CSDTC-SPD). It realizes phase detection as well as quantization noise cancellation in a single ramp generation. Bio: Xiang Gao received the B.E. degree from the Zhejiang University, Hangzhou, China, in 2004 and the M.Sc. and Ph.D. (cum laude) degrees from the University of Twente, Enschede, The Netherlands, in 2006 and 2010 respectively, both in electrical engineering. From 2010 to 2016, he was a principal engineer and design manager with Marvell Semiconductor, Santa Clara, CA, focusing on analog and RF IC design for wireless transceivers.
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Prof. Vadim Issakov

On March 28, the IEEE MTT-S Japan/Kansai/Nagoya Chapter hosted the DML Lecture (Distinguished Microwave Lecture), in which Prof. Vadim Issakov of the Technische Universität Braunschweig (TU-Braunschweig) gave a lecture on his millimeter-wave radar research.
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Tapping into the 300 GHz Band with an Innovative CMOS Transmitter

New phased-array transmitter design overcomes common problems of CMOS technology in the 300 GHz band, as reported by scientists from Tokyo Tech. Thanks to its remarkable area efficiency, low power consumption, and high data rate, the proposed transmitter could pave the way to many technological applications in the 300 GHz band, including body and cell monitoring, radar, 6G wireless communications, and terahertz sensors.
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Combating Fractional Spurs in Phase Locked Loops to Improve Wireless System Performance in Beyond 5G

Two innovative design techniques lead to substantial improvements in performance in fractional-N phase locked loops (PLLs), report scientists from Tokyo Tech. The proposed methods are aimed to minimize unwanted signals known as fractional spurs, which typically plague PLLs used in many modern radar systems and wireless transceivers. These efforts could open doors to technological improvements in wireless communication, autonomous vehicles, surveillance, and tracking systems in beyond 5G era.
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ISSCC 2024, 6 presentations

Presentation in ISSCC 2024. Regular Session Dingxin Xu, et al.,“A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter” Chun Wang, et al.,“A 236-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS” Forum Presentation Kenichi Okada, “Low-Power Fractional-N Digital PLL Design Techniques” Keito Yuasa, Yi Zhang, and Chenxin Liu will present their work in Student Research Preview.
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Party

Congratulations!! Chun Wang-san and Dinxin Xu-san!!
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Webinars for Young Excellence: Interpolation: Creating a reference free smooth A/D conversion

Title: Webinars for Young Excellence: Interpolation: Creating a reference free smooth A/D conversion Presenter: Prof. Akira Matsuzawa Abstract: Conventional A/D conversion is performed by comparing the input signal voltage with the reference voltage. On the other hand, by dividing and comparing the output voltages of two amplifiers with different reference voltages with the same input signal voltage, it was found that A/D conversion can be performed. This A/D conversion method is called interpolated A/D conversion. This conversion method enables smooth A/D conversion with a small DNL without adjusting the gain of the amplifier or the reference voltage, and also enables low power consumption by reducing the number of amplifiers. In this talk, we will introduce not only the principles and effects of interpolated A/D conversion, but also conceptual methods in circuit development, such as generalization by intuition and formulation that gave rise to unique A/D conversion methods. A resistive-interpolated Bi-CMOS ADC was developed for home HDTV receivers. A capacitive-interpolated CMOS ADC reduced the power consumption to 1/8 of other ADCs was developed for the portable digital video equipment such as a handy camcorder. A gate-width interpolation CMOS ADC achieved ultra-high-speed operation of 400 MS/s and 1/10 the power consumption of the other ADCs. It is embedded on the world’s first one-chip Mixed Signal SoC for DVD and contributed higher performance and lower cost of DVD recorders. In this talk, we would like you to understand that the interpolated A/D conversion method is not just an idea but was created for the development of A/D converters with high performance and low power in order to realize the new electronic devices. Akira Matsuzawa received B.S., M.S., and Ph.D. degrees in EE from Tohoku University, Sendai, Japan, in 1976, 1978, and 1997. In 1978, he joined Panasonic, and in 2003, joined Tokyo Institute of Technology as a full professor, and in 2018, became professor emeritus and CEO of Tech Idea. He has been developing video-rate ADCs, mixed-signal SoCs and millimeter-wave CMOS transceivers. In 2022, he received IEEE Donald. O. Pederson award in Solid-State Circuits. He is an IEEE Fellow since 2002 and Life-Fellow since 2023.
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