ISSCC 2024, 6 presentations

Presentation in ISSCC 2024.

Regular Session

  • Dingxin Xu, et al.,“A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter”
  • Chun Wang, et al.,“A 236-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS”

Forum Presentation

  • Kenichi Okada, “Low-Power Fractional-N Digital PLL Design Techniques”

Keito Yuasa, Yi Zhang, and Chenxin Liu will present their work in Student Research Preview.