ISSCC 2024で6件発表

ISSCC 2024で発表します！

Regular Session

• Dingxin Xu, et al.,“A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter”
• Chun Wang, et al.,“A 236-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS”

Forum Presentation

• Kenichi Okada, “Low-Power Fractional-N Digital PLL Design Techniques”

湯浅景斗さん、Yi Zhangさん、Chenxin Liuさんが、Student Research Previewで発表します。