新着情報

研究室見学 by Zoom

5/15 14:00から研究室見学 by Zoomを開催しますので、ご興味のある方は岡田 okada@ee.e.titech.ac.jp まで連絡くださいー! p.s. コロナに負けずに、みんながんばっています!
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ISSCC 2020

ISSCC 2020 Atsushi SHIRANE: ISSCC Student Research Preview, Committee Member Zheng LI: ISSCC Student Research Preview Speaker Yuncheng ZHANG: ISSCC Student Research Preview Speaker Haosheng ZHANG: IEEE SSCS Predoctoral Achievement AwardKenichi OKADA: ISSCC Evening Panel, Quiz Show Image from iOS (1)
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All Japan Alumni @ ISSCC2020

All Japan Alumni @ ISSCC2020◆日時:2020年2月16日 (日) 17:45 - 21:00 ◆会場:(第一部)Pacific A/B Room at the San Francisco Marriott Marquis (第二部)レストラン Fang (660 Howard St, San Francisco, CA 94105) (徒歩 7分) https://goo.gl/maps/yVCatP8ero62 ◆プログラム (第一部) 17:45 開場(出欠確認,案内配布,名刺交換,意見交換) @マリオット 18:15 あいさつ(趣旨説明) ・IEEE SSCS Japan Industry Contribution Award表彰式 ・集合写真撮影・案内など 18:30 移動開始 (第二部) 19:00 意見交換会開始 21:00 終了 (もちろん一部だけのご参加でも結構です)
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Prof. Fa Dai

Prof. Fa Dai, South China University of Technology (SCUT), came to our lab at November 8th, 2019! Welcome!!! 1108_1
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JSSCで2件発表します!

JSSC2019 Haosheng Zhang, Herdian Hans, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shigeyoshi Goka, Shinya Yanagimachi, and Kenichi Okada,“ULPAC: A Miniaturized Ultralow-Power Atomic Clock,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 11, pp. 3135-3148, Nov. 2019.https://doi.org/10.1109/JSSC.2019.2941004Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada,“A 265-uW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, Dec. 2019.https://doi.org/10.1109/JSSC.2019.2936967Congratulations!
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OB会

OB会のお酒而今 純米大吟醸 1.8L 久保田 万寿 1.8L 鍋島 純米大吟醸 山田錦 1.8L 磯自慢 特本 (秘蔵寒造り) 1.8L 鳳凰美田 赤判 1.8L 田酒 720ml 森伊蔵 720ml MOUTAI 500ml クラフトビール各種
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JSSCで3件発表します!

JSSC 2019 Jian PANG, et al.“A 28-GHz CMOS Phased-Array Transceiver Based on LO Phas-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio” Yun WANG, et al.“A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS” Jian PANG, et al.“A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance” Congratulations!
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Self Introduction (Kota Hatano)

Hi! My name is Kota Hatano, who is a new Master student in this lab. I was born and grew up in Shizuoka, Japan. It is famous for Mt.Fuji and green tea. ファイル_001-min I got my Bachelor degree in Tokyo University of Science. My graduation thesis topic is optical communication. So, I’m studying for RF circuit design and I want to improve my knowledge and skills in this area. ファイル_002-min **In term of my hobby, I am interested in baseball (MLB: Los Angeles Dodgers, NPB: Chiba Lotte Marines), watching Anime (e.g. Neon Genesis Evangelion, Yuruyuri), attending a concert of an artist and a voice actor that I like (e.g. LiSA, Inori Minase), trying new ramen restaurants and so on. I hope that I could make good friendship with guys in this lab. ファイル_003-min ファイル_004-min ファイル_005-min ファイル_006-min ファイル_007-min It’s a pleasure to become a member of Okada laboratory. Thank you!
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VLSI Circuit Symposium 2019 Paper Acceptance

We got 1 paper accepted to VLSI Circuit Symposium 2019. (Haosheng Zhang)“0.2mW 70 fsrms-jitter injection-locked PLL using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur”
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