Welcome to Okada's page: Tokyo Institute of Technology (Tokyo Tech)


japanese

Kenichi Okada (Ph.D.)

Professor

Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology

2-12-1-S3-28, Ookayama, Meguro-ku, Tokyo 152-8552 JAPAN
Tel: +81-3-5734-2258
Fax: +81-3-5734-3764
Email: okada at ee.e.titech.ac.jp
Office: Ookayama Campus, South Bldg. 3, 812 and 314

Education:
B.E. in School of Electronic Engineering, Kyoto University, Japan. (March 1998)
M.E. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan. (March 2000)
Ph.D. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan. (March 2003)


Work Experience:
Research Fellow of the Japan Society for the Promotion of Science (JSPS) (April 2000 - March 2003).
Assistant Professor, Precision and Intelligence Laboratory, Tokyo Institute of Technology (April 2003 - Sept. 2005).
Assistant Professor, Integrated Research Institute, Tokyo Institute of Technology (Oct. 2005 - Mar. 2007).
Associate Professor, Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology (April 2007 - Mar. 2019).
Associate Professor, Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology (April 2016 - Mar. 2019).
Professor, Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology (April 2019 -).


Research Projects:
5G phased-array transceiver
1Tb/s millimeter-wave Wireless Communication
60GHz CMOS RF Circuits for 300Gb/s Wireless Communication
Millimeter-wave Antenna, High-frequency PCB design
Satellite Communication
Atomic Clock
IoT battery-less transceiver
Synthesizable PLL
All-Digital PLL, Injection-Locked PLL
Terahertz Wireless Communication, Terahertz Imaging
Reconfigurable analog RF circuits
Modeling and Optimization of On-chip Spiral Inductor

Keywords: CMOS, RF, Oscillator, VCO, PLL, LNA, PA, Mixer, AD-PLL, Sub-sampling PLL, Injection-Locked PLL, Synthesizable PLL, Device characterization, De-embedding, Millimeter-wave, Wireless transceiver, Radar, Imager, Wi-Fi, WiGig, 60GHz, 5G, Phased array, 28GHz, 39GHz, Cellular, Smart phone, Antenna, Phased-array antenna, 5G antenna, High-frequency PCB design, Satellite communication, Satellite constellation, LEO, GEO, GPS, Terahertz, 300GHz, Atomic clock, ULPAC, CSAC, IoT, IoE, Bluetooth, Bluetooth Low Energy, BLE, Battery-less sensor node


Recruit:
I have a lot of foregin students from China, Korea, Indonesia, Thailand, Vietnam, Saudi Arabia, Taiwan, Turkey, Jordan, India, Cuba, Singapore, Australia, Canada, Norway, Sweden, Bangladesh, Kenia, Laos, Swiss, etc.

- Tsinghua University, Beijing University, Beihang University, Beijing Institute of Technology, Zhejiang University, Fudan University, Dalian University of Technology, Xi'an Jiaotong University, Xidian University, UESTC, USTC, Southeast University, and many
- Bandung Institute of Technology
- Chulalongkorn University, Thammasat University

I can support your living cost depending on your ability. Please contact me.


Academic Degree:
Doctor of Infomatics (Kyoto Univ.)
March 24, 2003
"A Study on Modeling and Analysis for Performance Fluctuation of CMOS Integrated Circuits"


Academic Society:
IEEE(Senior Member), IEICE(Senior Member), IPSJ, JSAP


Professional Activities and Service
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Design Contest Committee Member (2008), Design Contest Committee Chair (2009), Tutorial Chair (2011)
IEEE Solid-State Circuits Society Japan Chapter, Treasurer (2007.1-2008.12), Secretary (2009.1-2010.12)
IEEE International Solid-State Circuits Conference (ISSCC) 2012-2016, Technical Program Committee Member (2011.3-2016.3)
IEEE European Solid-State Circuits Conference (ESSCIRC) 2014-, Technical Program Committee Member (2013.9-)
IEEE Journal of Solid-State Circuits (JSSC), Guest Editor (2015.7)
IEEE Symposium on VLSI Circuits (VLSI Circuits) 2016-, Technical Program Committee Member (2015.8-), Evening Panel Co-Chair (2017.8-2019.8)
IEEE Journal of Solid-State Circuits (JSSC), Guest Editor (2015.12)
IEEE Journal of Solid-State Circuits (JSSC), Associate Editor (2015.9-)
IEEE Solid-State Circuits Society, Webinar "CMOS Millimeter-wave Transceiver Design" (2018.12.12)
IEEE Solid-State Circuits Society, Distinguished Lecturer (2019.1-2020.12)
IEEE Transactions on Microwave Theory and Techniques (T-MTT), Associate Editor (2019.10-)
IEEE Radio Frequency Integrated Circuits Symposium (RFIC) 2020, Technical Program Committee Member (2019.11-)


Major Publications All Publications
Yun Wang, et al.,
     "A 39-GHz 64-Element Phased-Array Transceiver with Built-in Phase and Amplitude Calibration for Large-Array 5G NR in 65-nm CMOS,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 5, pp. 1249-1269, May 2020.
Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada
     "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019.
Haosheng Zhang, Herdian Hans, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shigeyoshi Goka, Shinya Yanagimachi, and Kenichi Okada,
     "ULPAC: A Miniaturized Ultralow-Power Atomic Clock,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 11, pp. 3135-3148, Nov. 2019.
Jian Pang, et al.,
     "A 28GHz CMOS Phased-Array Transceiver Based on LO Phase Shifting Architecture with Gain Invariant Phase Tuning for 5G New Radio,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1228-1242, May 2019.
Yun Wang, et al.,
     "A 60-GHz 3.0Gb/s Spectrum Efficient BPOOK Transceiver for Low-power Short-range Wireless in 65-nm CMOS,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1363-1374, May 2019.
Jian Pang, et al.,
     "A 50.1Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay with Calibration of LO Feed-Through and I/Q Imbalance,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1375-1390, May 2019.
Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada,
     "A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 256-257, Feb. 2019.
Jian Pang, et al.,
     "A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 344-345, Feb. 2019.
Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shinya Yanagimachi, and Kenichi Okada,
     "Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2x10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 462-463, Feb. 2019.
Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, and Kenichi Okada,
     "A Sub-mW Fractional-N ADPLL with FOM of -246dB for IoT Applications,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018.
Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu and Kenichi Okada,
     "A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, Dec. 2018.
Korkut Kaan Tokgoz, et al.,
     "A 120Gb/s 16QAM CMOS Millimeter-Wave Wireless Transceiver,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 168-169, Feb. 2018.
Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, and Akira Matsuzawa,
     "A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FoM of -246dB for IoT Applications in 65nm CMOS,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 246-247, Feb. 2018.
Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, and Akira Matsuzawa,
     "An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 444-445, Feb. 2018.
Rui Wu, et al.,
     "64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 11, pp. 2871-2891, Nov. 2017.
Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, and Akira Matsuzawa,
     "A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 150-151, Feb. 2017.
Jian Pang, et al.,
     "A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 424-425, Feb. 2017.
Kenichi Okada,
     "Synthesizable PLL Using Digital Standard Cell Library,"(invited)
     IEEE International Solid-State Circuits Conference (ISSCC) Forum, San Francisco, CA, pp.503-505, Feb. 2017.
Zule Xu, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 3.6GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 10, pp. 2345-2356, Oct. 2016.
Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, and Akira Matsuzawa,
     "A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Interpolator with an FoM of -250dB,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 7, pp. 1630-1640, July 2016.
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 6, pp. 1385-1397, June 2016.
Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, and Akira Matsuzawa,
     "A Low-Power Low-Noise mm-Wave Sub-Sampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 5, pp. 1246-1260, May 2016.
Korkut Kaan Tokgoz, et al.,
     "A 56Gb/s W-Band CMOS Wireless Transceiver,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 242-243, Feb. 2016.
Rui Wu, et al.,
     "A 42Gb/s 60GHz CMOS Transceiver for IEEE802.11ay,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 248-249, Feb. 2016.
Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, and Akira Matsuzawa,
     "A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 252-253, Feb. 2015.
Rui Wu, et al.,
     "A HCI-Healing 60GHz CMOS Transceiver,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 350-351, Feb. 2015.
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tooru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 440-441, Feb. 2015.
Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, and Akira Matsuzawa,
     "A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 1, pp. 68-80, Jan. 2015.
Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa,
     "A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-synchronized Gating Injection Technique for Software-defined Radios,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 9, pp. 1984-1994, Sep. 2014.
Kenichi Okada, et al.,
     "A 64-QAM 60GHz CMOS Transceiver with 4-Channel Bonding,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 346-347, Feb. 2014.
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 266-267, Feb. 2014.
Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 1, pp. 50-60, Jan. 2014.
Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa,
     "A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 7, pp. 1710-1720, July 2013.
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 0.022mm2 970µW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.248-249, Feb. 2013.
Wei Deng, Kenichi Okada, and Akira Matsuzawa,
     "Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp.429-440, Feb. 2013.
Kenichi Okada, et al.,
     "Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver with Low-Power Analog and Digital Baseband Circuitry,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 1, pp.46-65, Jan. 2013.
Kenichi Okada, et al.,
     "A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver With Low-Power Analog and Digital Baseband Circuitry,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.218-219, Feb. 2012.
Kenichi Okada, et al.,
     "A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 12, pp. 2988-3004, Dec. 2011.
Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, and Akira Matsuzawa,
     "A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 11, pp. 2635-2649, Nov. 2011.
Kenichi Okada, et al.,
     "A 60GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE 802.15.3c,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.160-161, Feb. 2011.
Kenichi Okada,
     "Reconfigurable RF CMOS Circuits for Cognitive Radios,"(invited)
     IEEE International Solid-State Circuits Conference (ISSCC) Forum, San Francisco, CA, pp.512-513, Feb. 2010.
Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, and Kazuya Masu,
     "A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 4, pp.1020-1029, April 2008.
Hiroyuki Ito, Junpei Inoue, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu,
     "On-Chip Transmission Line for Long Global Interconnects,"
     IEEE International Electron Devices Meeting (IEDM), pp.677-680, 2004.
Kenichi Okada, Kento Yamaoka, and Hidetoshi Onodera,
     "A Statistical Gate-Delay Model Considering Intra-Gate Variability,"
     IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.908-913, 2003.


Honors and Awards
Young Investigator Award, IEICE (2002)
Yasujiro Niwa Outstanding Paper Award (2004)
Yamashita Memorial Award, Information Processing Society of Japan (2004)
Ericsson Young Scientist Award (2004)
IEEE A-SSCC Outstanding Design Award (2006)
ADMETA Technical Achievement Award 2006 (2007)
IEEE/ACM ASP-DAC, Special Feature Award (2011)
MEXT Young Scientists' Prize (2011)
IEEE A-SSCC Best Design Award (2011)
IEEE SSCS Japan Chapter Academic Research Award (2012)
IEEE SSCS Japan Chapter Academic Research Award (2013)
IEEE/ACM ASP-DAC, Best Design Award (2014)
JSPS Prize (2014)
IEEE/ACM ASP-DAC, Best Design Award (2015)
Suematsu Yasuharu Award (2015)
IEEE/ACM ASP-DAC, Best Design Award (2017)
MEXT Prizes for Science and Technology (2017)
IEEE RFIT, Best Paper Award (2017)
IEEE SSCS Kansai Chapter Academic Research Award (2018)
IEICE Best Paper Award (2018)
IEEE SSCS Japan Chapter Academic Research Award (2019)
IEEE RFIC Symposium, Best Student Paper Award (2019)
IEICE Achievement Award (2019)
DOCOMO Mobile Science Award (2019)
IEEE/ACM ASP-DAC, Prolific Author Award (2020)
Kenjiro Takayanagi Achivement Award (2020)
KDDI Foundation Award (2020)
IEEE CICC Best Paper Award (2020)
(more than 50 international and domestic awards)


Birth:
February, 1975



Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology

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