Welcome to Okada's page: Department of Physical Electronics, Tokyo Institute of Technology


japanese

Kenichi Okada (Ph.D.)

Associate Professor

Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology

2-12-1-S3-28, Ookayama, Meguro-ku, Tokyo 152-8552 JAPAN
Tel: +81-3-5734-2258
Fax: +81-3-5734-3764
Email: okada at ssc.pe.titech.ac.jp
Office: Ookayama Campus, South Bldg. 3, 812 and 314

Education:
B.E. in School of Electronic Engineering, Kyoto University, Japan. (March 1998)
M.E. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan. (March 2000)
Ph.D. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan. (March 2003)


Work Experience:
Research Fellow of the Japan Society for the Promotion of Science (April 2000 - March 2003).
Assistant Professor, Precision and Intelligence Laboratory, Tokyo Institute of Technology (April 2003 - Sept. 2005).
Assistant Professor, Integrated Research Institute, Tokyo Institute of Technology (Oct. 2005 - Mar. 2007).
Associate Professor, Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology (April 2007-).
Associate Professor, Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology (April 2016-).


Research Projects:
IoT battery-less transceiver
5G transceiver
1Tb/s millimeter-wave Wireless Communication
60GHz CMOS RF Circuits for 300Gb/s Wireless Communication
Synthesizable PLL
All-Digital PLL, Injection-Locked PLL
Terahertz Wireless Communication, Terahertz Imaging
Reconfigurable analog RF circuits
Atomic Clock
Modeling and Optimization of On-chip Spiral Inductor

Keywords: CMOS, RF, Oscillator, VCO, PLL, LNA, PA, Mixer, Sub-sampling PLL, ADC-PLL, Injection-Locked PLL, device characterization, de-embedding, Millimeter-wave, 60GHz, Wireless transceiver, 5G, Cellular, Smart phone, Wi-Fi, WiGig IoT, IoE, Battery-less sensor node


Recruit:
I have a lot of foregin students from China, Korea, Tailand, Vietnum, Saudi Arabia, etc.
I can support your living cost depending on your ability. Please contact me.


Academic Degree:
Doctor of Infomatics (Kyoto Univ.)
March 24, 2003
"A Study on Modeling and Analysis for Performance Fluctuation of CMOS Integrated Circuits"


Academic Society:
IEEE, IEICE, IPSJ, JSAP


Major Publications All Publications
Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, and Akira Matsuzawa,
     "A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 150-151, Feb. 2017.
Jian Pang, et al.,
     "A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 424-425, Feb. 2017.
Zule Xu, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 3.6GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 10, pp. 2345-2356, Oct. 2016.
Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, and Akira Matsuzawa,
     "A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Interpolator with an FoM of -250dB,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 7, pp. 1630-1640, July 2016.
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 6, pp. 1385-1397, June 2016.
Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, and Akira Matsuzawa,
     "A Low-Power Low-Noise mm-Wave Sub-Sampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 5, pp. 1246-1260, May 2016.
Korkut Kaan Tokgoz, et al.,
     "A 56Gb/s W-Band CMOS Wireless Transceiver,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 242-243, Feb. 2016.
Rui Wu, et al.,
     "A 42Gb/s 60GHz CMOS Transceiver for IEEE802.11ay,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 248-249, Feb. 2016.
Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, and Akira Matsuzawa,
     "A 0.048-mm2 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 252-253, Feb. 2015.
Rui Wu, et al.,
     "A HCI-Healing 60GHz CMOS Transceiver,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 350-351, Feb. 2015.
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tooru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 440-441, Feb. 2015.
Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, and Akira Matsuzawa,
     "A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 1, pp. 68-80, Jan. 2015.
Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa,
     "A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-synchronized Gating Injection Technique for Software-defined Radios,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 9, pp. 1984-1994, Sep. 2014.
Kenichi Okada, et al.,
     "A 64-QAM 60GHz CMOS Transceiver with 4-Channel Bonding,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 346-347, Feb. 2014.
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 0.0066mm2 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 266-267, Feb. 2014.
Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 1, pp. 50-60, Jan. 2014.
Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa,
     "A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 7, pp. 1710-1720, July 2013.
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,
     "A 0.022mm2 970µW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.248-249, Feb. 2013.
Wei Deng, Kenichi Okada, and Akira Matsuzawa,
     "Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp.429-440, Feb. 2013.
Kenichi Okada, et al.,
     "Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver with Low-Power Analog and Digital Baseband Circuitry,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 1, pp.46-65, Jan. 2013.
Kenichi Okada, et al.,
     "A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver With Low-Power Analog and Digital Baseband Circuitry,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.218-219, Feb. 2012.
Kenichi Okada, et al.,
     "A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 12, pp. 2988-3004, Dec. 2011.
Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, and Akira Matsuzawa,
     "A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 11, pp. 2635-2649, Nov. 2011.
Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada,
     Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, and Akira Matsuzawa,
     "A 60GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE 802.15.3c,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.160-161, Feb. 2011.
Shoichi Hara, Kenichi Okada, and Akira Matsuzawa,
     "10MHz to 7GHz Quadrature Signal Generation Using a Divide-by-4/3, -3/2, -5/3, -2, -5/2, -3, -4, and -5 Injection-Locked Frequency Divider,"
     IEEE Symposium on VLSI Circuits, Honolulu, HI, pp.51-52, June 2010.
Kenichi Okada,
     "Reconfigurable RF CMOS Circuits for Cognitive Radios,"(invited)
     IEEE International Solid-State Circuits Conference (ISSCC) Forum, San Francisco, CA, pp.512-513, Feb. 2010.
Kenichi Okada, You Nomiyama, Rui Murakami, and Akira Matsuzawa,
     "A 0.114-mW Dual-Conduction Class-C CMOS VCO with 0.2-V Power Supply,"
     IEEE Symposium on VLSI Circuits, Kyoto, pp.228-229, June 2009.
Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, and Kazuya Masu,
     "A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 4, pp.1020-1029, April 2008.
Hiroyuki Ito, Makoto Kimura, Kenichi Okada, and Kazuya Masu,
     "A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers,"
     IEEE Symposium on VLSI Circuits, Kyoto, Japan, pp.136-137, June 2007.
Kenichi Okada, Hirotaka Sugawara, Hiroyuki Ito, Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Tatsuya Ito, and Kazuya Masu,
     "On-Chip High-Q Variable Inductor Using Wafer-Level Chip-Scale Package Technology,"
     IEEE Transactions on Electron Devices, Vol. 53, No. 9, pp. 2401-2406, Sep. 2006.
Hiroyuki Ito, Junpei Inoue, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu,
     "On-Chip Transmission Line for Long Global Interconnects,"
     IEEE International Electron Devices Meeting (IEDM), pp.677-680, 2004.
Kenichi Okada, Kento Yamaoka, and Hidetoshi Onodera,
     "A Statistical Gate-Delay Model Considering Intra-Gate Variability,"
     IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.908-913, 2003.


Professional Activities and Service
International Conference on Solid State Devices and Materials, Steering Committee Member (2003.9-2004.9)
Workshop on Synthesis and System Integration of Mixed Technologies, Technical Program Committee (2006)
IEICE Transactions, Special Section on VLSI Design Technology in the Sub-100 nm Era (March 2006), Editorial Committee Member
IEICE Transactions on Electronics, Special Section on VLSI Design and CAD Algorithm (Dec. 2006), Editorial Committee Member
IEICE Transactions on Electronics, Special Section on VLSI Design and CAD Algorithm (Dec. 2007), Editorial Committee Member
IEICE Transactions on Electronics, Special Section on VLSI Design and CAD Algorithm (Dec. 2008), Editorial Committee Member
IEICE Transactions, Special Section of Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa (Apr. 2008), Editorial Committee Member
IEEE Solid-State Circuits Society Japan Chapter, Treasurer (2007.1-2008.12)
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Design Contest Committee Member (2008)
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Design Contest Committee Chair (2009)
IEEE Solid-State Circuits Society Japan Chapter, Secretary (2009.1-2010.12)
IEICE Transactions, Special Section on VLSI Design and CAD Algorithm (Dec. 2009), Editorial Committee Member
IEICE Transactions, Special Section on Circuits and Design Techniques for Advanced Large Scale Integration (March 2010), Editorial Committee Member
IEICE Transactions, Special Section on VLSI Design and CAD Algorithm (Dec. 2010), Editorial Committee Member
IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tutorial Chair (2011)
International Conference on Solid State Devices and Materials, Technical Program Committee Member (2010.12-2011.11)
IEICE Transactions, Special Section on Solid-State Circuit Design -Architecture, Circuit, Device and Design Methodology (April 2012), Editorial Committee Member
IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Technical Program Committee Member (2011.2-)
IEEE International Solid-State Circuits Conference (ISSCC) 2012, Technical Program Committee Member (2011.3-2012.3)
IEEE International Solid-State Circuits Conference (ISSCC) 2013, Technical Program Committee Member (2012.3-2013.3)
IEEE International Solid-State Circuits Conference (ISSCC) 2014, Technical Program Committee Member (2013.3-2014.3)
IEEE European Solid-State Circuits Conference (ESSCIRC) 2014, Technical Program Committee Member (2013.9-2014.9)
IEEE International Solid-State Circuits Conference (ISSCC) 2015, Technical Program Committee Member (2014.3-2015.3)
IEEE European Solid-State Circuits Conference (ESSCIRC) 2015, Technical Program Committee Member (2014.9-2015.9)
IEEE International Solid-State Circuits Conference (ISSCC) 2016, Technical Program Committee Member (2015.3-2016.3)
IEEE Journal of Solid-State Circuits (JSSC), Guest Editor (2015.7)
IEEE Journal of Solid-State Circuits (JSSC), Guest Editor (2015.12)
IEEE Symposium on VLSI Circuits (VLSI Circuits) 2016, Technical Program Committee Member (2015.8-2016.8)
IEEE European Solid-State Circuits Conference (ESSCIRC) 2016, Technical Program Committee Member (2015.9-2016.9)
IEEE Journal of Solid-State Circuits (JSSC), Associate Editor (2015.9-)
IEEE Symposium on VLSI Circuits (VLSI Circuits) 2017, Technical Program Committee Member (2016.8-2017.8)


Honors and Awards
Young Investigator Award, IEICE (2002)
Yasujiro Niwa Outstanding Paper Award (2004)
Yamashita Memorial Award, Information Processing Society of Japan (2004)
Ericsson Young Scientist Award (2004)
IEEE A-SSCC Outstanding Design Award (2006)
ADMETA Technical Achievement Award 2006 (2007)
IEEE/ACM ASP-DAC, Special Feature Award (2011)
MEXT Young Scientists' Prize (2011)
IEEE A-SSCC Best Design Award (2011)
IEEE SSCS Japan Chapter Academic Research Award (2012)
IEEE SSCS Japan Chapter Academic Research Award (2013)
IEEE/ACM ASP-DAC, Best Design Award (2014)
JSPS Prize (2014)
IEEE/ACM ASP-DAC, Best Design Award (2015)
Suematsu Yasuharu Award (2015)
IEEE/ACM ASP-DAC, Best Design Award (2017)
MEXT Prizes for Science and Technology (2017)
(more than 30 international and domestic awards)


Birth:
February, 1975



Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology

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