Kenichi Okada (Ph.D.)

Education:

B.E. in School of Electronic Engineering, Kyoto University, Japan. (March 1998)

M.E. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan. (March 2000)

Ph.D. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University,Japan (March 2003)

Work Experience:

Research Fellow of the Japan Society for the Promotion of Science(April 2000 - March 2003).

Assistant Professor, Precision and Intelligence Laboratory, Tokyo Institute of Technology(April 2003 - Sept. 2005).

Assistant Professor, Integrated Research Institute, Tokyo Institute of Technology(Oct. 2005 - Mar. 2007).

Associate Professor, Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology(April 2007-).

Areas of Interest:

60GHz CMOS RF Circuits for 40Gbps Wireless Communication

Reconfigurable analog RF circuits

GHz interconnect technology in Si ULSI

Modeling and Analysis of Manufacturing Fluctuation

Modeling and Optimization of On-chip Spiral Inductor

Signal Integrity Analysis

Recruit:

I have a lot of foregin students from China, Korea, Tailand, Vietnum, Saudi Arabia, etc.

I can support your living cost depending on your ability. Please contact me.

Academic Degree:

Doctor of Infomatics (Kyoto Univ.)

March 24, 2003

"A Study on Modeling and Analysis for Performance Fluctuation of CMOS Integrated Circuits"

Academic Society:

IEEE, IEICE, IPSJ, JSAP

Major Publications All Publications

Kenichi Okada, et al.,
     "A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver With Low-Power Analog and Digital Baseband Circuitry,"
     IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2012.

Kenichi Okada, et al.,
     "A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 12, pp. 2988-3004, Dec. 2011.

Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, and Akira Matsuzawa,
     "A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 11, pp. 2635-2649, Nov. 2011.

Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada,
     Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, and Akira Matsuzawa,
     "A 60GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE 802.15.3c,"
     IEEE International Solid-State Circuits Conference (ISSCC), pp.160-161, San Francisco, CA, Feb. 2011.

Shoichi Hara, Kenichi Okada, and Akira Matsuzawa,
     "10MHz to 7GHz Quadrature Signal Generation Using a Divide-by-4/3, -3/2, -5/3, -2, -5/2, -3, -4, and -5 Injection-Locked Frequency Divider,"
     IEEE Symposium on VLSI Circuits, Honolulu, HI, pp.51-52, June 2010.

Kenichi Okada,
     "Reconfigurable RF CMOS Circuits for Cognitive Radios,"(invited)
     IEEE International Solid-State Circuits Conference (ISSCC) Forum, pp.512-513, San Francisco, CA, Feb. 2010.

Kenichi Okada, You Nomiyama, Rui Murakami, and Akira Matsuzawa,
     "A 0.114-mW Dual-Conduction Class-C CMOS VCO with 0.2-V Power Supply,"
     IEEE Symposium on VLSI Circuits, pp.228-229, Kyoto, June 2009.

Takeshi Ito, Kenichi Okada, and Kazuya Masu,
     "Characterization of On-Chip Multi-Port Inductors for Small-Area RF Circuits,"
     IEEE Transactions on Circuits and Systems I, Vol. 56, No. 8, pp. 1590-1597, Aug. 2009.

Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, and Kazuya Masu,
     "A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications,"
     IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 4, pp.1020-1029, April 2008.

Hiroyuki Ito, Makoto Kimura, Kenichi Okada, and Kazuya Masu,
     "A 8-Gbps Low-Latency Multi-Drop On-Chip Transmission Line Interconnect with 1.2-mW Two-Way Transceivers,"
     IEEE Symposium on VLSI Circuits, pp.136-137, Kyoto, Japan, June 2007.

Kenichi Okada, Hirotaka Sugawara, Hiroyuki Ito, Kazuhisa Itoi, Masakazu Sato, Hiroshi Abe, Tatsuya Ito, and Kazuya Masu,
     "On-Chip High-Q Variable Inductor Using Wafer-Level Chip-Scale Package Technology,"
     IEEE Transactions on Electron Devices, Vol. 53, No. 9, pp. 2401-2406, Sep. 2006.

Hiroyuki Ito, Junpei Inoue, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu,
     "On-Chip Transmission Line for Long Global Interconnects,"
     IEEE International Electron Devices Meeting (IEDM), pp.677-680, 2004.

Kenichi Okada, Kento Yamaoka, and Hidetoshi Onodera,
     "A Statistical Gate-Delay Model Considering Intra-Gate Variability,"
     IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.908-913, 2003.

Professional Activities and Service

International Conference on Solid State Devices and Materials, Steering Committee Member (2003.9-2004.9)

Workshop on Synthesis and System Integration of Mixed Technologies, Technical Program Committee (2006)

IEICE Transactions, Special Section on VLSI Design Technology in the Sub-100 nm Era (March 2006), Editorial Committee Member

IEICE Transactions on Electronics, Special Section on VLSI Design and CAD Algorithm (Dec. 2006), Editorial Committee Member

IEICE Transactions on Electronics, Special Section on VLSI Design and CAD Algorithm (Dec. 2007), Editorial Committee Member

IEICE Transactions on Electronics, Special Section on VLSI Design and CAD Algorithm (Dec. 2008), Editorial Committee Member

IEICE Transactions, Special Section of Selected Papers from the 20th Workshop on Circuits and Systems in Karuizawa (Apr. 2008), Editorial Committee Member

IEEE Solid-State Circuits Society Japan Chapter, Treasurer (2007.1-2008.12)

IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Design Contest Committee Member (2008)

IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Design Contest Committee Chair (2009)

IEEE Solid-State Circuits Society Japan Chapter, Secretary (2009.1-2010.12)

IEICE Transactions, Special Section on VLSI Design and CAD Algorithm (Dec. 2009), Editorial Committee Member

IEICE Transactions, Special Section on Circuits and Design Techniques for Advanced Large Scale Integration (March 2010), Editorial Committee Member

IEICE Transactions, Special Section on VLSI Design and CAD Algorithm (Dec. 2010), Editorial Committee Member

IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Tutorial Chair (2011)

International Conference on Solid State Devices and Materials, Technical Program Committee Member (2010.12-2011.11)

IEICE Transactions, Special Section on Solid-State Circuit Design -Architecture, Circuit, Device and Design Methodology (April 2012), Editorial Committee Member

IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Technical Program Committee Member (2011.2-)

IEEE International Solid-State Circuits Conference (ISSCC), Technical Program Committee Member (2011.3-)

Honors and Awards

Young Investigator Award, IEICE (2002)

Yasujiro Niwa Outstanding Paper Award (2004)

Yamashita Memorial Award, Information Processing Society of Japan (2004)

Ericsson Young Scientist Award (2004)

IEEE A-SSCC Outstanding Design Award (2006)

ADMETA Technical Achievement Award 2006 (2007)

IEEE A-SSCC Best Design Award (2011)

(more than 30 international and domestic awards)

Birth:

February, 1975