Prof. Wei Deng and Prof. Xiang Gao

清華大のWei Deng先生(SSCS DL)と浙江大学のXiang Gao先生が、東工大を訪問されました。

5/2(木) 15:30-16:30 Prof. Wei Deng (SSCS DL講演会)

“Joint Radar-communication CMOS Transceiver”

16:30-17:30 Prof. Xiang Gao

“Frac-N Sampling PLL with Phase Detection and Quantization Noise Cancellation in a Single Ramp Generation”

★各講演の詳細

(Talk 1) Speaker: Prof. Wei Deng (Tsinghua University)

Title: Joint Radar-communication CMOS Transceiver: From System Architecture to Circuit Design

Abstract: Recent years, millimeter-wave and Terahertz radar systems for sensing and radio systems for communication have attracted substantial attention both from the academia and industry. In addition, there is an increasing demanding for fusing both the hardware platform and frequency band of the radar and radio system, which has advantages of energy efficiency, performance optimization, spectrum sharing/efficiency, compact size, interference management, and the overall cost, as compared to assembling of two distinct systems. This lecture will introduce the current and future trends in the emerging joint radar-communication CMOS transceiver from system architecture to circuit design.

Bio: Wei Deng received the B.S. and M.S. degrees from the University of Electronic Science and Technology of China (UESTC), China, in 2006 and 2009, respectively, and the Ph.D. degree from the Tokyo Institute of Technology, Japan, in 2013. He was with Apple Inc., Cupertino, CA, USA, working on RF, mm-wave, and mixed-signal IC design for wireless transceivers and Apple A-series processors. Currently he is with Tsinghua University, Beijing, China, as an Associate Professor. His research interests include RF, mm-wave, terahertz, and mixed-signal integrated circuits and systems for wireless communications, sensing, and imaging systems. He has authored or co-authored more than 160 IEEE journal and conference articles. Dr. Deng is a TPC Member of ISSCC, VLSI, A-SSCC, CICC and ESSCIRC. He has been an Associate Editor and a Guest Editor of the IEEE Solid-State Circuits Letters (SSC-L), a Guest Editor of the IEEE Journal of Solid-state Circuits (JSSC), and a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS).

(Talk 2) Speaker: Prof. Xiang Gao (Zhejiang University)

Title: Frac-N Sampling PLL with Phase Detection and Quantization Noise Cancellation in a Single Ramp Generation

Abstract: Conventional PLLs detecting phase error in the time domain using a phase frequency detector often suffer from poor in-band phase noise due to the limited phase detector (PD) gain. The (Sub-)Sampling PLL is becoming a popular low jitter PLL architecture due to high gain of the SSPD. However, the high gain SSPD has a limited linear detection range, which is a challenge in fractional-N operation with the quantization noise. This talk presents a SPLL design with a merged constant-slope digital-to-time converter(DTC) and sampling phase detector (CSDTC-SPD). It realizes phase detection as well as quantization noise cancellation in a single ramp generation.

Bio: Xiang Gao received the B.E. degree from the Zhejiang University, Hangzhou, China, in 2004 and the M.Sc. and Ph.D. (cum laude) degrees from the University of Twente, Enschede, The Netherlands, in 2006 and 2010 respectively, both in electrical engineering. From 2010 to 2016, he was a principal engineer and design manager with Marvell Semiconductor, Santa Clara, CA, focusing on analog and RF IC design for wireless transceivers. From 2016 to 2018, he was an Engineering Director with Credo Semiconductor, Milpitas, CA, working on high-speed SerDes. Since August 2018, he has been a Faculty member at Institute of VLSI Design, Zhejiang University, China. He is an IEEE senior member, and TPC member of RFIC(2014-current)、CICC(2016-2023) and ISSCC(2015-2019, 2024-current).