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Novel Architecture Can Reduce Noise-Induced Jitters in Digital Technology

Jitters are a common shortcoming of modern electronic devices using a high-frequency digital signal. While oversampling phase-locked loops (OSPLLs) can expand the loop bandwidth, effectively reducing jitter, conventional OSPLLs suffer from high jitter in noisy signal peak areas. Tokyo Tech researchers have instead suggested and demonstrated a non-uniform OSPLL that can efficiently suppress jitter through adaptive loop gain calibration. This novel architecture leads to more economical and power-efficient devices than conventional OSPLLs.
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ISSCC 2023, 6 papers will be presented

Publication in ISSCC 2023. Regular Session Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration” Dongwon You, et al., “A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler” Xi Fu, et al., “A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low Earth Orbit Small Satellite Constellation” Plenary Talk Prof. Matsuzawa, “Shape the World With Mixed-Signal Integrated Circuits – Past, Present, and Future” Chun Wang and Dingxin Xu will present their work in Student Research Preview.
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ISSCC 2022, 4 papers will be presented

Publication in ISSCC 2022. Regular Session Jian Pang, et al., “A Power-Efficient 24-71GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36-dB Inter-Band Blocker Rejection for 5G NR” Xi Fu, et al., “A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation” Michihiro Ide and Dongwon You will present their work in Student Research Preview.
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ISSCC 2021, 5 papers will be presented

Publication in ISSCC 2021. Regular Session Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth” Ibrahim Abdo, et al., “A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS” Zheng Li, Zheng Sun, and Michihiro Ide will present their work in Student Research Preview.
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Prof. Fa Dai

Prof. Fa Dai, South China University of Technology (SCUT), came to our lab at November 8th, 2019! Welcome!!! 1108_1
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Prof. Tsung-Hsien Lin

Prof. Tsung-Hsien Lin, National Taiwan University (NTU), came to our lab at October 25th, 2019! IMG_20191025_175824
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Prof. Nan SUN

Great talk from Prof. Nan SUN, UT Austin! New Ingredients in the Pot - Rethink Analog IC Design -
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Prof. Omeed Momeni

Prof. Omeed Momeni(University of California, Davis ) visited our lab! He is very famous for mm-Wave and Terahertz Signal Generation, Amplification, and Beam Steering in Silicon.
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Prof. R. Bogdan Staszewski

Prof. R. Bogdan Staszewski from University College Dublin visited our Lab. on Saturday, July 14. He gave a seminar about AD-PLL. The seminar from Prof. R. Bogdan Staszewski. End Session Group Photo with Prof. R. Bogdan Staszewski.
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Prof. Flynn

Prof. Flynn(University of Michigan) visited our lab! He is very famous for ADC design.
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Prof. Patrick Yue

Prof. Patrick Yue (HKUST) visited our labHe is very famous for VLC and gave a talk about this! DSC09607
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Prof. Huei Wang

Prof. Huei Wang (National Taiwan University) visited our lab! P1080054 He is very famous for CMOS RFIC design, but this time he gave a talk about “Harmonic Radar Development for Bee Searching”! 
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ISSCC Student-Research Preview Award

Mr. Maki (now working for Panasonic) wins ISSCC Student-Research Preview Award(Honarable Montion)!! Shotaro Maki, Yuuki Seo, Kenichi Okada, and Akira Matsuzawa, “A 64QAM 60GHz Transceiver with Automatic Image Calibration,” IEEE International Solid-State Circuits Conference (ISSCC) Student Research Preview, San Francisco, CA, Feb. 2016.
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