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ISSCC 2026で4件発表

Tue, 25 Nov 2025 15:57:00 +0900

ISSCC 2026で発表します！

Forum Presentation

Kenichi Okada, “Exploration of 6G FR3 for Coverage, Capacity, and Sensing in Edge AI Era”

Regular Session

Daxu Zhang, et al., “A 9.7GHz Self-Linearized-VCO-Based FMCW Chirp Generator Achieving 1.56GHz/µs Slope and 0.57µs Duration with 0.094% rms Frequency Error”

Dongfan Xuさん、Minghao Fanさんが、Student Research Previewで発表します。

ISSCC 2025で6件発表

Fri, 07 Feb 2025 13:15:00 +0900

ISSCC 2025で発表します！

Forum Presentation

Kenichi Okada, “Foldable Phased-Array Transceivers for Satellite Communications”

Regular Session

Yuncheng Zhang, et al.,“A Power-Efficient CORDIC-less Digital Polar Transmitter Using 1b DSM-Based PA Supporting 256-QAM”
Sena Kato, et al.,“A 256-Element Ka-Band CMOS Phased-Array Receiver Using Switch-Type Quadrature-Hybrid-First Architecture for Small Satellite Constellations” (白根研)

山崎雄大さん、Minzhe Tangさん、Daxu Zhangさんが、Student Research Previewで発表します。

VLSI Symposiumで3件発表

Sun, 23 Jun 2024 12:41:00 +0000

IEEE Symposium on VLSI Technology & CircuitsでChenxin Liuさん、加藤さん、Yi Zhangさんが発表しました！

Chenxin Liu “A 640-Gb/s 4x4-MIMO D-Band CMOS Transceiver Chipset”
Sena Kato “A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer”
Yi Zhang “A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond”

ISSCC 2024で6件発表

Mon, 22 Jan 2024 22:39:41 +0900

ISSCC 2024で発表します！

Regular Session

Dingxin Xu, et al.,“A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter”
Chun Wang, et al.,“A 236-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS”

Forum Presentation

Kenichi Okada, “Low-Power Fractional-N Digital PLL Design Techniques”

湯浅景斗さん、Yi Zhangさん、Chenxin Liuさんが、Student Research Previewで発表します。

ISSCC 2023で6件発表

Thu, 01 Dec 2022 15:36:48 +0000

ISSCC 2023で発表します！

Regular Session

Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration”
Dongwon You, et al., “A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler”
Xi Fu, et al., “A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low Earth Orbit Small Satellite Constellation”

Plenary Talk

Prof. Matsuzawa, “Shape the World With Mixed-Signal Integrated Circuits – Past, Present, and Future”

Chun WangさんとDingxin Xuさんが、Student Research Previewで発表します。

ISSCC 2022で4件発表

Wed, 01 Dec 2021 15:36:48 +0000

ISSCC 2022で発表します！

Regular Session

Jian Pang, et al., “A Power-Efficient 24-71GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36-dB Inter-Band Blocker Rejection for 5G NR”
Xi Fu, et al., “A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation”

井出倫滉とDongwon Youさんが、Student Research Previewで発表します。

ISSCC 2021で5件発表

Tue, 01 Dec 2020 15:36:48 +0000

ISSCC 2021で発表します！

Regular Session

Junjun Qiu, et al., “A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth”
Ibrahim Abdo, et al., “A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS”

Zheng Liさん、Zheng Sunさん、井出倫滉さんが、Student Research Previewで発表します。

ISSCC 2020

Thu, 23 Jan 2020 17:33:08 +0000

ISSCC 2020 Atsushi SHIRANE: ISSCC Student Research Preview, Committee Member

Zheng LI: ISSCC Student Research Preview Speaker

Yuncheng ZHANG: ISSCC Student Research Preview Speaker

Haosheng ZHANG: IEEE SSCS Predoctoral Achievement AwardKenichi OKADA: ISSCC Evening Panel, Quiz Show

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ISSCCで発表しました

Mon, 25 Feb 2019 00:15:03 +0000

ISSCCで3件発表しました！
http://isscc.org/

Session 16.1 (Hanli Liu)
“A 265-μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS"従来の半分以下の消費電力で動作するAD-PLL
(jp)https://www.titech.ac.jp/news/2019/043373.html
(en)https://www.titech.ac.jp/english/news/2019/043428.html

Session 21.1 (Jian Pang)
“A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR”
5G用ミリ波フェーズドアレイ無線機
(jp) https://www.titech.ac.jp/news/2019/043378.html
(en) https://www.titech.ac.jp/english/news/2019/043432.html

Session 29.4 (Haosheng Zhang)
“Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2x10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping”
60mW動作可能な小型原子時計
(jp) https://www.titech.ac.jp/news/2019/043571.html
(en) https://www.titech.ac.jp/english/news/2019/043524.html

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ISSCC 2019で５件発表します！

Wed, 05 Dec 2018 15:47:19 +0000

ISSCC 2019
Program
(1) Hanli LIU, et al.,“A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS” (Session 16.1)

(2) Jian PANG, et al.,“A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR” (Session 21.1)

(3)Haosheng ZHANG, et al.,“Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2×10-12 Long-Term Allan Deviation Using Cesium Coherent Population Trappin” (Session 29.4)

また、Bangan Liuさん、Yun Wangさんが、Student Research Previewで発表をします。

ISSCC 2018で４件発表します！

Tue, 19 Dec 2017 15:06:48 +0000

ISSCC 2018
Program

Hanli LIUさんは2件発表の快挙です！Korkutさんはデモもやります。世界最速の120Gbpsを現地でお披露目の予定です！

(1)Hanli LIU, et al.,“A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FOM of -246dB for IoT Applications in 65nm CMOS” (Session 15.1)

新型DTC回路(Digital-to-Time Converter)により、世界で初めて1mW以下の消費電力でBLE等の無線機に利用可能なデジタルPLLを実現しました。

(2)Hanli LIU, et al.,“An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS” (Session 28.2)

世界最小電力で動作するBluetooth Low-Energy(BLE)無線機を実現しました。送信時2.9mW、受信時2.3mWです。

(3)Korkut Kaan TOKGOZ, et al.,“A 120Gb/s 16QAM CMOS Millimeter-Wave Wireless Transceiver” (Session 9.6)

世界最高速の120Gb/sの無線機をCMOS集積回路として実現しました。

また、Bangan Liuさんが、Student Research Previewで発表をします。

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ISSCC 2017で4件発表します！

Sun, 22 Jan 2017 14:56:52 +0000

ISSCC 2017
Program

(Regular session)Jian Pang, et al.,"A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance" Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, and Akira Matsuzawa"A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO" (Forum)Kenichi Okada"Synthesizable PLL Using Digital Standard Cell Library" (Student Research Preview)Korkut Kaan Tokgoz, Jian Pang, Shotaro Maki, Kenichi Okada, and Akira Matsuzawa

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publication on 東京科学大学 岡田研究室

ISSCC 2026で4件発表

ISSCC 2025で6件発表

VLSI Symposiumで3件発表

ISSCC 2024で6件発表

ISSCC 2023で6件発表

ISSCC 2023で発表します！

ISSCC 2022で4件発表

ISSCC 2022で発表します！

ISSCC 2021で5件発表

ISSCC 2021で発表します！

ISSCC 2020

ISSCCで発表しました

ISSCC 2019で５件発表します！

ISSCC 2018で４件発表します！

ISSCC 2017で4件発表します！

publication on 東京科学大学岡田研究室