Kenichi Okada

Contents

Professor

Department of Electrical and Electronic Engineering
School of Engineering
Tokyo Institute of Technology, Tokyo, Japan

okadaee.e.titech.ac.jp

Biography

Kenichi Okada received the B.E., M.E., and Ph.D. degrees in communications and computer engineering from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively. From 2000 to 2003, he was a Research Fellow of the Japan Society for the Promotion of Science in Kyoto University. In 2003, he joined Tokyo Institute of Technology as an Assistant Professor, where he is currently a Professor of electrical and electronic engineering. He has authored or co-authored more than 500 journal and conference papers. His current research interests include millimeter-wave and terahertz CMOS wireless transceivers for 20/28/39/60/77/79/100/300GHz for 5G, WiGig, satellite and future wireless systems, digital PLL, synthesizable PLL, atomic clock, and ultra-low-power wireless transceivers for Bluetooth Low-Energy, and sub-GHz applications.

Prof. Okada is a member of the Institute of Electrical and Electronics Engineers (IEEE), the Institute of Electronics, Information and Communication Engineers (IEICE), the Information Processing Society of Japan (IPSJ), and the Japan Society of Applied Physics (JSAP). He was a recipient or co-recipient of the Ericsson Young Scientist Award in 2004, the A-SSCC Outstanding Design Award in 2006 and 2011, the ASP-DAC Special Feature Award in 2011 and Best Design Award in 2014 and 2015, the MEXT Young Scientists’ Prize in 2011, the JSPS Prize in 2014, the Suematsu Yasuharu Award in 2015, the MEXT Prizes for Science and Technology in 2017, the RFIT Best Paper Award in 2017, the IEICE Best Paper Award in 2018, the RFIC Symposium Best Student Paper Award in 2019, the IEICE Achievement Award in 2019, the DOCOMO Mobile Science Award in 2019, the IEEE/ACM ASP-DAC Prolific Author Award in 2020, the Kenjiro Takayanagi Achievement Award in 2020, the KDDI Foundation Award in 2020, the IEEE CICC, Best Paper Award in 2020, the IEEE ISSCC Author-Recognition Award in 2023, and more than 50 other international and domestic awards. He is a Fellow of IEEE. He is/was a member of the technical program committees of IEEE International Solid-State Circuits Conference (ISSCC), VLSI Circuits Symposium, European Solid-State Circuits Conference (ESSCIRC), Radio Frequency Integrated Circuits Symposium (RFIC), Asian Solid-State Circuits Conference (A-SSCC), and he is/was also Guest Editors and an Associate Editor of IEEE Journal of Solid-State Circuits (JSSC), an Associate Editor of IEEE Transactions on Microwave Theory and Techniques (T-MTT), a Distinguished Lecturer of the IEEE Solid-State Circuits Society (SSCS).

short bio

Prof. Kenichi Okada received the B.E., M.E., and Ph.D. degrees from Kyoto University, Kyoto, Japan, in 1998, 2000, and 2003, respectively. He joined Tokyo Institute of Technology in 2003, and he is now Professor. His research interests include millimeter-wave and terahertz wireless transceiver, and digital PLL. He is a Fellow of IEEE, and he has worked for ISSCC, JSSC, VLSI Circuits, ESSCIRC, A-SSCC and RFIC Symposium.

Education

B.E. in School of Electronic Engineering, Kyoto University, Japan. (March 1998)
M.E. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan. (March 2000)
Ph.D. in Department of Communications and Computer Engineering, Graduate school of Informatics, Kyoto University, Japan. (March 2003)

Academic Degree

Doctor of Informatics (Kyoto Univ.) March 24, 2003

“A Study on Modeling and Analysis for Performance Fluctuation of CMOS Integrated Circuits”

Work Experience

Research Fellow of the Japan Society for the Promotion of Science (JSPS) (April 2000 - March 2003).
Assistant Professor, Precision and Intelligence Laboratory, Tokyo Institute of Technology (April 2003 - Sept. 2005).
Assistant Professor, Integrated Research Institute, Tokyo Institute of Technology (Oct. 2005 - Mar. 2007).
Associate Professor, Department of Physical Electronics, Graduate School of Science and Engineering, Tokyo Institute of Technology (April 2007 - Mar. 2019).
Associate Professor, Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology (April 2016 - Mar. 2019).
Professor, Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology (April 2019 -).

Research Projects

Phased-array transceiver for 5G, 6G, 7G
Terahertz Wireless Communication, Terahertz Imaging
1Tb/s Millimeter-wave Wireless Communication
Satellite Communication
All-Digital PLL, Synthesizable PLL, Injection-Locked PLL
Millimeter-wave Antenna, High-frequency PCB design
Quantum computing/sensing, Cryo-CMOS, Atomic Clock
IoT battery-less transceiver
Reconfigurable analog RF circuits
Modeling and Optimization of On-chip Spiral Inductor

Keywords

CMOS, RF, Oscillator, VCO, PLL, LNA, PA, Mixer, AD-PLL, Sub-sampling PLL, Injection-Locked PLL, Synthesizable PLL, Device characterization, De-embedding, Millimeter-wave, Wireless transceiver, Radar, Imager, Wi-Fi, WiGig, 60GHz, 5G, Beyond 5G, 6G, 7G, Phased array, 28GHz, 39GHz, Cellular, Smart phone, Antenna, Phased-array antenna, 5G antenna, High-frequency PCB design, Satellite communication, Satellite constellation, LEO, GEO, GPS, Terahertz, 300GHz, Quantum computer, Quantum computing, Quantum sensing, Quantum communication, Cryogenic CMOS, Cryo-CMOS, Atomic clock, ULPAC, CSAC, IoT, IoE, Bluetooth, Bluetooth Low Energy, BLE, Battery-less sensor node

Recruitment

I accept new students widely from all over the world. I can support your living cost depending on your ability. Please contact me.

Academic Society

IEEE(Fellow), IEICE(Senior Member), IPSJ, JSAP

Professional Activities and Service

IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), Design Contest Committee Member (2008), Design Contest Committee Chair (2009), Tutorial Chair (2011)
IEEE Solid-State Circuits Society Japan Chapter, Treasurer (2007.1-2008.12), Secretary (2009.1-2010.12)
IEEE International Solid-State Circuits Conference (ISSCC) 2012-2016, Technical Program Committee Member (2011.3-2016.3)
IEEE European Solid-State Circuits Conference (ESSCIRC) 2014-2022, Technical Program Committee Member (2013.9-2022.9)
IEEE Journal of Solid-State Circuits (JSSC), Guest Editor (2015.7)
IEEE Symposium on VLSI Circuits (VLSI Circuits) 2016-, Technical Program Committee Member (2015.8-), Evening Panel Co-Chair (2017.8-2019.8), Focus Session and Invited Paper Chair (2023.8-2025.8)
IEEE Journal of Solid-State Circuits (JSSC), Guest Editor (2015.12)
IEEE Journal of Solid-State Circuits (JSSC), Associate Editor (2015.9-2022.9)
IEEE Solid-State Circuits Society, Webinar “CMOS Millimeter-wave Transceiver Design” (2018.12.12)
IEEE Solid-State Circuits Society, Distinguished Lecturer (2019.1-2020.12)
IEEE Transactions on Microwave Theory and Techniques (T-MTT), Associate Editor (2019-2021)
IEEE Radio Frequency Integrated Circuits Symposium (RFIC) 2020-, Technical Program Committee Member (2019.11-), Steering Committee Member (2022.5-)
IEEE Asian Solid-State Circuits Conference (A-SSCC) 2022-, Technical Program Committee Member (2022.2-)

Selected Publications

Chun Wang, et al.,“A Sub-THz Full-Duplex Phased-Array Transceiver with Self-Interference Cancellation and LO Feedthrough Suppression,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 59, No. 4, pp. 978-992, Apr. 2024.
Yuncheng Zhang, et al.,“A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 59, No. 4, pp. 993-1005, Apr. 2024.
Kenichi Okada,“Low-Power Fractional-N Digital PLL Design Techniques,"(invited) IEEE International Solid-State Circuits Conference (ISSCC) Forum, San Francisco, CA, Feb. 2024.
Chun Wang, et al.,“A 236-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2024.
Dingxin Xu, et al.,“A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2024.
Xi Fu, et al.,“A Low-Power Radiation-Hardened Ka-Band CMOS Phased-Array Receiver for Small Satellite Constellation,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 59, No. 2, pp. 349-363, Feb. 2024.
Xi Fu, et al.,“A Low-Power 256-Element Ka-Band CMOS Phased-Array Receiver with On-Chip Distributed Radiation Sensors for Small Satellite Constellations,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 58, No. 12, pp. 3380-3395, Dec. 2023.
Yudai Yamazaki, et al.,“A 37-43.5GHz Phase and Amplitude Detection Circuit with 0.049-degree and 0.036-dB Accuracy for 5G Phased-Array Calibration Using Transformer-Based Injection-Enhanced ILFD,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 58, No. 10, pp. 2851-2860, Oct. 2023.
Zheng Li, et al.,“A 39-GHz CMOS Bi-Directional Doherty Phased-Array Beamformer Using Shared-LUT DPD with Inter-Element Mismatch Compensation Technique for 5G Base-Station,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 58, No. 4, pp. 901-914, Apr. 2023.
Junjun Qiu, et al.,“A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain Boosted PD and Loop Gain Calibration,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2023.
Dongwon You, et al.,“A Small-Satellite-Mounted 256-Element Ka-Band CMOS Phased-Array Transmitter Achieving 63.8dBm EIRP Under 26.6W Power Consumption Using Single/Dual Circular Polarization Active Coupler,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2023.
Xi Fu, et al.,“A 2.95mW/element Ka-band CMOS Phased-Array Receiver Utilizing On-Chip Distributed Radiation Sensors in Low Earth Orbit Small Satellite Constellation,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2023.
Yi Zhang, Jian Pang, Zheng Li, Minzhe Tang, Yijing Liao, Ashbir Aviat Fadila, Atsushi Shirane, and Kenichi Okada,“A Power-Efficient CMOS Multi-Band Phased-Array Receiver Covering 24-71GHz Utilizing Harmonic-Selection Technique with 36-dB Inter-Band Blocker Tolerance for 5G NR,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57 , No. 12, pp. 3617-3630, Dec. 2022.
Ibrahim Abdo, et al.,“A Bi-Directional 300GHz-Band Phased-Array Transceiver in 65nm CMOS with Outphasing Transmitting Mode and LO Emission Cancellation,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 8, pp. 2292-2308, Aug. 2022.
Michihiro Ide, Atsushi Shirane, Kiyoshi Yanagisawa, Dongwon You, Jian Pang, and Kenichi Okada,“A 28-GHz Phased-Array Relay Transceiver for 5G Network Using Vector-Summing Backscatter with 24-GHz Wireless Power and LO Transfer,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 4, pp. 1211-1223, Apr. 2022.
Jian Pang, et al.,“A Power-Efficient 24-71GHz CMOS Phased-Array Receiver Utilizing Harmonic-Selection Technique Supporting 36-dB Inter-Band Blocker Rejection for 5G NR,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2022.
Xi Fu, et al.,“A 3.4mW/element Radiation-Hardened Ka-Band CMOS Phased-Array Receiver Utilizing Magnetic-Tuning Phase Shifter for Small Satellite Constellation,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, Feb. 2022.
Yun Wang, et al.,“A Ka-Band SATCOM Transceiver in 65-nm CMOS with High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 57, No. 2, pp. 356-370, Feb. 2022.
Junjun Qiu, et al.,“A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 56, No. 12, pp. 3741-3755, Dec. 2021.
Jian Pang, et al.,“A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 56, No. 4, pp. 1310-1326, Apr. 2021.
Ibrahim Abdo, et al.,“A 300GHz-Band Phased-Array Transceiver Using Bi-Directional Outphasing and Hartley Architecture in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 316-317, Feb. 2021.
Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang, Yun Wang, Atsushi Shirane, and Kenichi Okada,“A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth,” IEEE International Solid-State Circuits Conference (ISSCC), pp. 454-455, Feb. 2021.
Jian Pang, et al.,“A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 9, pp. 2371-2386, Sept. 2020.
Hiroshi Hamada, et al.,“300-GHz-band 120-Gb/s Wireless Front-end Based on InP-HEMT PAs and Mixers,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 9, pp. 2316-2335, Sept. 2020.
Yun Wang, et al.,“A 39-GHz 64-Element Phased-Array Transceiver with Built-in Phase and Amplitude Calibration for Large-Array 5G NR in 65-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 55, No. 5, pp. 1249-1269, May 2020.
Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada“A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Sub-sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 12, pp. 3478-3492, Dec. 2019.
Haosheng Zhang, Herdian Hans, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shigeyoshi Goka, Shinya Yanagimachi, and Kenichi Okada,“ULPAC: A Miniaturized Ultralow-Power Atomic Clock,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 11, pp. 3135-3148, Nov. 2019.
Jian Pang, et al.,“A 28GHz CMOS Phased-Array Transceiver Based on LO Phase Shifting Architecture with Gain Invariant Phase Tuning for 5G New Radio,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1228-1242, May 2019.
Yun Wang, et al.,“A 60-GHz 3.0Gb/s Spectrum Efficient BPOOK Transceiver for Low-power Short-range Wireless in 65-nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1363-1374, May 2019.
Jian Pang, et al.,“A 50.1Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay with Calibration of LO Feed-Through and I/Q Imbalance,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 54, No. 5, pp. 1375-1390, May 2019.
Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, and Kenichi Okada,“A 265-µW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 256-257, Feb. 2019.
Jian Pang, et al.,“A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 344-345, Feb. 2019.
Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shinya Yanagimachi, and Kenichi Okada,“Ultra-Low-Power Atomic Clock for Satellite Constellation with 2.2x10^-12 Long-Term Allan Deviation Using Cesium Coherent Population Trapping,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 462-463, Feb. 2019.
Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, and Kenichi Okada,“A Sub-mW Fractional-N ADPLL with FOM of -246dB for IoT Applications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, pp. 3540-3552, Dec. 2018.
Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu and Kenichi Okada,“A DPLL-Centric Bluetooth Low-Energy Transceiver with a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65nm CMOS,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 53, No. 12, pp. 3672-3687, Dec. 2018.
Korkut Kaan Tokgoz, et al.,“A 120Gb/s 16QAM CMOS Millimeter-Wave Wireless Transceiver,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 168-169, Feb. 2018.
Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, and Akira Matsuzawa,“A 0.98mW Fractional-N ADPLL Using 10b Isolated Constant-Slope DTC with FoM of -246dB for IoT Applications in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 246-247, Feb. 2018.
Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, and Akira Matsuzawa,“An ADPLL-Centric Bluetooth Low-Energy Transceiver with 2.3mW Interference-Tolerant Hybrid-Loop Receiver and 2.9mW Single-Point Polar Transmitter in 65nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 444-445, Feb. 2018.
Rui Wu, et al.,“64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 52, No. 11, pp. 2871-2891, Nov. 2017.
Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, and Akira Matsuzawa,“A 0.42ps-Jitter -241.7dB-FOM Synthesizable Injection-Locked PLL with Noise-Isolation LDO,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 150-151, Feb. 2017.
Jian Pang, et al.,“A 128-QAM 60GHz CMOS Transceiver for IEEE802.11ay with Calibration of LO Feedthrough and I/Q Imbalance,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 424-425, Feb. 2017.
Kenichi Okada,“Synthesizable PLL Using Digital Standard Cell Library,"(invited) IEEE International Solid-State Circuits Conference (ISSCC) Forum, San Francisco, CA, pp.503-505, Feb. 2017.
Zule Xu, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,“A 3.6GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 10, pp. 2345-2356, Oct. 2016.
Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, and Akira Matsuzawa,“A Fractional-N Sub-Sampling PLL Using a Pipelined Phase-Interpolator with an FoM of -250dB,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 7, pp. 1630-1640, July 2016.
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,“A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using Digital Sub-Sampling Architecture,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 6, pp. 1385-1397, June 2016.
Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, and Akira Matsuzawa,“A Low-Power Low-Noise mm-Wave Sub-Sampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE802.11ad,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 51, No. 5, pp. 1246-1260, May 2016.
Korkut Kaan Tokgoz, et al.,“A 56Gb/s W-Band CMOS Wireless Transceiver,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 242-243, Feb. 2016.
Rui Wu, et al.,“A 42Gb/s 60GHz CMOS Transceiver for IEEE802.11ay,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 248-249, Feb. 2016.
Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, and Akira Matsuzawa,“A 0.048-mm² 3-mW Synthesizable Fractional-N PLL with a Soft Injection-Locking Technique,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 252-253, Feb. 2015.
Rui Wu, et al.,“A HCI-Healing 60GHz CMOS Transceiver,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 350-351, Feb. 2015.
Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tooru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,“A 2.2-GHz -242dB-FoM 4.2-mW ADC-PLL Using Digital Sub-Sampling Architecture,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 440-441, Feb. 2015.
Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, and Akira Matsuzawa,“A Fully Synthesizable All-digital PLL with Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-resolution Digital Varactor Using Gated Edge Injection Technique,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 50, No. 1, pp. 68-80, Jan. 2015.
Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa,“A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-synchronized Gating Injection Technique for Software-defined Radios,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 9, pp. 1984-1994, Sep. 2014.
Kenichi Okada, et al.,“A 64-QAM 60GHz CMOS Transceiver with 4-Channel Bonding,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 346-347, Feb. 2014.
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,“A 0.0066mm² 780µW Fully Synthesizable PLL with a Current Output DAC and an Interpolative-Phase Coupled Oscillator using Edge Injection Technique,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp. 266-267, Feb. 2014.
Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,“A Compact, Low Power and Low Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 49, No. 1, pp. 50-60, Jan. 2014.
Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, and Akira Matsuzawa,“A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 7, pp. 1710-1720, July 2013.
Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, and Akira Matsuzawa,“A 0.022mm² 970µW Dual-Loop Injection-Locked PLL with -243dB FOM Using Synthesizable All-Digital PVT Calibration Circuits,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.248-249, Feb. 2013.
Wei Deng, Kenichi Okada, and Akira Matsuzawa,“Class-C VCO with Amplitude Feedback Loop for Robust Start-up and Enhanced Oscillation Swing,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 2, pp.429-440, Feb. 2013.
Kenichi Okada, et al., “Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver with Low-Power Analog and Digital Baseband Circuitry,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 48, No. 1, pp.46-65, Jan. 2013.
Kenichi Okada, et al.,“A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver With Low-Power Analog and Digital Baseband Circuitry,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.218-219, Feb. 2012.
Kenichi Okada, et al., “A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 12, pp. 2988-3004, Dec. 2011.
Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, and Akira Matsuzawa,“A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 46, No. 11, pp. 2635-2649, Nov. 2011.
Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, and Akira Matsuzawa,“A 60GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE 802.15.3c,” IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, pp.160-161, Feb. 2011.
Kenichi Okada,“Reconfigurable RF CMOS Circuits for Cognitive Radios,"(invited) IEEE International Solid-State Circuits Conference (ISSCC) Forum, San Francisco, CA, pp.512-513, Feb. 2010.
Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, and Kazuya Masu,“A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications,” IEEE Journal of Solid-State Circuits (JSSC), Vol. 43, No. 4, pp.1020-1029, April 2008.
Hiroyuki Ito, Junpei Inoue, Shinichiro Gomi, Hideyuki Sugita, Kenichi Okada, and Kazuya Masu,“On-Chip Transmission Line for Long Global Interconnects,” IEEE International Electron Devices Meeting (IEDM), pp.677-680, 2004.
Kenichi Okada, Kento Yamaoka, and Hidetoshi Onodera,“A Statistical Gate-Delay Model Considering Intra-Gate Variability,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), pp.908-913, 2003.

Young Investigator Award, IEICE (2002)
Yasujiro Niwa Outstanding Paper Award (2004)
Yamashita Memorial Award, Information Processing Society of Japan (2004)
Ericsson Young Scientist Award (2004)
IEEE A-SSCC Outstanding Design Award (2006)
ADMETA Technical Achievement Award 2006 (2007)
IEEE/ACM ASP-DAC, Special Feature Award (2011)
MEXT Young Scientists’ Prize (2011)
IEEE A-SSCC Best Design Award (2011)
IEEE SSCS Japan Chapter Academic Research Award (2012)
IEEE SSCS Japan Chapter Academic Research Award (2013)
IEEE/ACM ASP-DAC, Best Design Award (2014)
JSPS Prize (2014)
IEEE/ACM ASP-DAC, Best Design Award (2015)
Suematsu Yasuharu Award (2015)
IEEE/ACM ASP-DAC, Best Design Award (2017)
MEXT Prizes for Science and Technology (2017)
IEEE RFIT, Best Paper Award (2017)
IEEE SSCS Kansai Chapter Academic Research Award (2018)
IEICE Best Paper Award (2018)
IEEE SSCS Japan Chapter Academic Research Award (2019)
IEEE RFIC Symposium, Best Student Paper Award (2019)
IEICE Achievement Award (2019)
DOCOMO Mobile Science Award (2019)
IEEE/ACM ASP-DAC, Prolific Author Award (2020)
Kenjiro Takayanagi Achievement Award (2020)
KDDI Foundation Award (2020)
IEEE CICC Best Paper Award (2020)
IEEE ICTA Best Paper Award (2020)
IEEE/ACM ASP-DAC, Best Design Award (2021)
IEEE ISSCC Outstanding Evening Session Award (2021)
IEEE Fellow (2023)
IEEE ISSCC Author-Recognition Award (2023)

(more than 50 international and domestic awards)

Contact Information

Email: okadaee.e.titech.ac.jp
Office: Tokyo Institute of Technology, Ookayama Campus, South Bldg. 3, Room 812
Address: 2-12-1-S3-28, Ookayama, Meguro-ku, Tokyo 152-8552 JAPAN
Tel: +81-3-5734-2258 (my room), +81-3-5734-3764 (Secretary/FAX)